1. Field of the Invention
This invention relates generally to programmable logic devices, and in particular to a device for loading data into an array of memory cells for a field programmable gate array.
2. Description of the Related Art
Field programmable gate arrays (FPGAs) typically include an array of memory cells for storing data that configures or defines the operation of the FPGA. The memory cells are typically static random access memory (SRAM) cells. FPGAs generally include an array of logic cells that are arranged in rows and columns. Each logic cell of a tile based SRAM FPGA comprises a configurable logic block and a programmable routing matrix, and has a group of configuration memory cells associated with it. The logic block responds to data inputs of the logic cell and generates the outputs of the logic cell. Each configurable logic block may perform any one of a variety of logic functions. The logic function performed by a particular logic block is defined by data stored in its associated group of configuration memory cells. The programmable routing matrix allows the inputs and outputs of the logic block to be coupled to the inputs and outputs of other logic blocks or the inputs and outputs of the FPGA. The couplings of the inputs and outputs of a particular logic block are similarly defined by data stored in its associated group of configuration memory cells. FPGAs also may include data storage memory cells, latches or flip-flops. However, the discussion of memory cells here will refer to configuration memory cells. The output of each memory cell may be set either high or low by storing a corresponding bit in the memory cell. Each memory cell is set using a configuration means. Setting all the memory cells of the FPGA is called configuring the FPGA. The data stored in the memory cells may be changed, or re-programmed, to modify the function of the FPGA. Storing a new set of data in the memory cells is referred to as reconfiguring the FPGA.
One problem with many existing FPGAs is that all the memory cells in the FPGA must be re-written in order to change the configuration of the FPGA. Programmability is a major feature of FPGAs and reconfiguration is particularly important during quality control testing of SRAM FPGAs. In order to test fully the FPGA, the manufacturer must repeatedly reconfigure the memory cells to test that the logic cell can perform all of the possible predetermined functions. Moreover, the memory cells are volatile memories. Therefore, the entire array of memory cells must be configured each time the FPGA is powered on.
The memory cells of the FPGA are arranged as an array of cells in columns and rows. The FPGA typically provides a single address register and a single data register for loading configuration data into memory cells. The data register is typically a serial input shift register. The use of a single address register and a single data register for accessing the memory cells saves space on the FPGA, which is critical since space is severely limited. However, the use of serial input shift registers increases the time required to load new configuration data into the memory cells in comparison to a parallel loading means.
The array of memory cells is reconfigured by loading data one row or column at a time. In the prior art, the data for each column of memory cells is loaded serially into a data shift register. When the data shift register is full, the data are transferred in parallel into the memory cells of a selected column of the array. Each stage of the shift register is coupled to a corresponding row of memory cells of the array. Thus, the first stage of the data shift register is coupled to the first memory cell of each column of the array. The FPGA selects a column of the array using the address register. The data shift register loads its data into the column of the array selected by the address register. Thus, if the configuration data are being loaded one bit per clock cycle, a number of clock cycles equal to the number of memory cells in a column of the array is the minimum number required to load data into a column of the array.
A typical FPGA can have more than a hundred thousand memory cells that must be written in order to configure the FPGA. Since each memory cell must be written to when the FPGA is reconfigured, the time required can be undesirably long. A column of the array may be hundreds of memory cells in length. The serial input to the data shift register requires at least this number of clock cycles to load a column of data into the data register and then into the array of memory cells. The time required to reconfigure an array is a particular problem during quality control testing since the array of memory cells must be repeatedly reconfigured. The time required for reconfiguration adds significant delay and expense to the testing of FPGAs. Further, some FPGA applications require that the FPGA be repeatedly and rapidly reconfigured during operation. Thus, there is a need for a device that reduces the time required to reconfigure FPGAs.